Uittreksel
| Originele taal-2 | Engels |
|---|---|
| Titel | Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2014), 24-28 March 2014, Dresden, Germany |
| Plaats van productie | Piscataway |
| Uitgeverij | Institute of Electrical and Electronics Engineers |
| Pagina's | 1-6 |
| ISBN van geprinte versie | 978-3-9815370-2-4 |
| DOI's | |
| Status | Gepubliceerd - 2014 |
| Evenement | 17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) - ICC, Dresden, Duitsland Duur: 24 mrt 2014 → 28 mrt 2014 Congresnummer: 17 https://www.date-conference.com/date14/ |
Congres
| Congres | 17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) |
|---|---|
| Verkorte titel | DATE 2014 |
| Land | Duitsland |
| Stad | Dresden |
| Periode | 24/03/14 → 28/03/14 |
| Ander | Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) |
| Internet adres |
Vingerafdruk
Citeer dit
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Exploiting expendable process-margins in DRAMs for run-time performance optimizations. / Chandrasekar, K.; Goossens, S.L.M.; Weis, C.; Koedam, M.L.P.J.; Akesson, K.B.; Wehn, N.; Goossens, K.G.W.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2014), 24-28 March 2014, Dresden, Germany. Piscataway : Institute of Electrical and Electronics Engineers, 2014. blz. 1-6.Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review
TY - GEN
T1 - Exploiting expendable process-margins in DRAMs for run-time performance optimizations
AU - Chandrasekar, K.
AU - Goossens, S.L.M.
AU - Weis, C.
AU - Koedam, M.L.P.J.
AU - Akesson, K.B.
AU - Wehn, N.
AU - Goossens, K.G.W.
PY - 2014
Y1 - 2014
N2 - Manufacturing-time process (P) variations and runtime voltage (V) and temperature (T) variations can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantial design-time PVT timing margins to guarantee correct DRAM functionality under worst-case operating conditions. Unfortunately, with technology scaling these timing margins have become large and very pessimistic for a majority of the manufactured DRAMs. While run-time variations are specific to operating conditions and as a result, their margins difficult to optimize, process variations are manufacturing-time effects and excessive process-margins can be reduced at run-time, on a per-device basis, if properly identified. In this paper, we propose a generic post-manufacturing performance characterization methodology for DRAMs that identifies this excess in process-margins for any given DRAM device at runtime, while retaining the requisite margins for voltage (noise) and temperature variations. By doing so, the methodology ascertains the actual impact of process-variations on the particular DRAM device and optimizes its access latencies (timings), thereby improving its overall performance. We evaluate this methodology on 48 DDR3 devices (from 12 DIMMs) and verify the derived timings under worst-case operating conditions, showing up to 33.3% and 25.9% reduction in DRAM read and write latencies, respectively.
AB - Manufacturing-time process (P) variations and runtime voltage (V) and temperature (T) variations can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantial design-time PVT timing margins to guarantee correct DRAM functionality under worst-case operating conditions. Unfortunately, with technology scaling these timing margins have become large and very pessimistic for a majority of the manufactured DRAMs. While run-time variations are specific to operating conditions and as a result, their margins difficult to optimize, process variations are manufacturing-time effects and excessive process-margins can be reduced at run-time, on a per-device basis, if properly identified. In this paper, we propose a generic post-manufacturing performance characterization methodology for DRAMs that identifies this excess in process-margins for any given DRAM device at runtime, while retaining the requisite margins for voltage (noise) and temperature variations. By doing so, the methodology ascertains the actual impact of process-variations on the particular DRAM device and optimizes its access latencies (timings), thereby improving its overall performance. We evaluate this methodology on 48 DDR3 devices (from 12 DIMMs) and verify the derived timings under worst-case operating conditions, showing up to 33.3% and 25.9% reduction in DRAM read and write latencies, respectively.
U2 - 10.7873/DATE.2014.186
DO - 10.7873/DATE.2014.186
M3 - Conference contribution
SN - 978-3-9815370-2-4
SP - 1
EP - 6
BT - Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2014), 24-28 March 2014, Dresden, Germany
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -