For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC backend structure when no appropriate precautions are taken. This paper presents an efficient method to describe the damage sensitivityof three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy-based, thus more accurate than stress-based criteria; (3) unlike recent fracture mechanics approaches, no initial defect size and location has to be assumed a priori. A mesh objectivity condition is formulated resulting from numerical experiments. The method is applied to advanced IC back-end structures, revealing not only the most critical back-end design but also the critical interfaces in the bond pad structures at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in the finite element code MSC.Marc. In this way, effects of e.g., packaging and wire bond loading at the global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low-kback-end structures. The obtained results are in good agreement with experimental observations.
|Tijdschrift||Microelectronics and Reliability : an International Journal and World Abstracting Service|
|Nummer van het tijdschrift||12|
|Status||Gepubliceerd - 2007|