Effective and efficient test architecture design for SOCs

Sandeep K. Goel, Erik J. Marinissen

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureHoofdstukAcademicpeer review

139 Citaten (Scopus)


This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs (test access mechanisms). For a given SOC, with specified parameters of modules and their tests, we design architectures which minimize the required ATE vector memory depth and test application time. In this paper, we formulate the problems of test architecture design both for modules with fixed- and flexible-length scan chains. Subsequently, we derive a formulation of an architecture-independent test time lower bound for SOCs and list the lower bound values for the 'ITC'02 SOC test benchmarks'. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and testrail architectures with serial and parallel test schedules. Experimental results for the 'ITC'02 SOC test benchmarks' show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
Originele taal-2Engels
TitelProceedings. International Test Conference 2002
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's10
ISBN van geprinte versie0-7803-7542-4
StatusGepubliceerd - 2002
Extern gepubliceerdJa
EvenementInternational Test Conference - Baltimore, Verenigde Staten van Amerika
Duur: 10 okt 200210 okt 2002


CongresInternational Test Conference
Land/RegioVerenigde Staten van Amerika


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