Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

Uittreksel

This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter is
not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz
MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.
TaalEngels
TitelIEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's547-550
Aantal pagina's4
ISBN van elektronische versie978-1-4673-6852-0
DOI's
StatusGepubliceerd - 29 mei 2017
Evenement50th IEEE International Symposium on Circuits and Systems (ISCAS 2017) - Baltimore, Verenigde Staten van Amerika
Duur: 28 mei 201731 mei 2017

Congres

Congres50th IEEE International Symposium on Circuits and Systems (ISCAS 2017)
Verkorte titelISCAS 2017
LandVerenigde Staten van Amerika
StadBaltimore
Periode28/05/1731/05/17

Vingerafdruk

Sampling
Transistors
Feedback
Bandwidth
Networks (circuits)
Compensation and Redress

Trefwoorden

    Citeer dit

    Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A., & van Roermund, A. H. M. (2017). Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. In IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA (blz. 547-550). Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ISCAS.2017.8050369
    Zhang, C. ; Breems, L.J. ; Radulov, G.I. ; Bolatkale, M. ; Liu, Qilong ; Hegt, J.A. ; van Roermund, A.H.M./ Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA. Piscataway : Institute of Electrical and Electronics Engineers, 2017. blz. 547-550
    @inproceedings{84e558deeddf40a6829777a5982de1e7,
    title = "Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs",
    abstract = "This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.",
    keywords = "Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC",
    author = "C. Zhang and L.J. Breems and G.I. Radulov and M. Bolatkale and Qilong Liu and J.A. Hegt and {van Roermund}, A.H.M.",
    year = "2017",
    month = "5",
    day = "29",
    doi = "10.1109/ISCAS.2017.8050369",
    language = "English",
    pages = "547--550",
    booktitle = "IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA",
    publisher = "Institute of Electrical and Electronics Engineers",
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    }

    Zhang, C, Breems, LJ, Radulov, GI, Bolatkale, M, Liu, Q, Hegt, JA & van Roermund, AHM 2017, Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. in IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA. Institute of Electrical and Electronics Engineers, Piscataway, blz. 547-550, Baltimore, Verenigde Staten van Amerika, 28/05/17. DOI: 10.1109/ISCAS.2017.8050369

    Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. / Zhang, C.; Breems, L.J.; Radulov, G.I.; Bolatkale, M.; Liu, Qilong; Hegt, J.A.; van Roermund, A.H.M.

    IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA. Piscataway : Institute of Electrical and Electronics Engineers, 2017. blz. 547-550.

    Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

    TY - GEN

    T1 - Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

    AU - Zhang,C.

    AU - Breems,L.J.

    AU - Radulov,G.I.

    AU - Bolatkale,M.

    AU - Liu,Qilong

    AU - Hegt,J.A.

    AU - van Roermund,A.H.M.

    PY - 2017/5/29

    Y1 - 2017/5/29

    N2 - This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

    AB - This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

    KW - Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC

    U2 - 10.1109/ISCAS.2017.8050369

    DO - 10.1109/ISCAS.2017.8050369

    M3 - Conference contribution

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    BT - IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA

    PB - Institute of Electrical and Electronics Engineers

    CY - Piscataway

    ER -

    Zhang C, Breems LJ, Radulov GI, Bolatkale M, Liu Q, Hegt JA et al. Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. In IEEE International Symposium on Circuits and Systems 2017 (ISCAS), 28-31 May 2017, Baltimore, USA. Piscataway: Institute of Electrical and Electronics Engineers. 2017. blz. 547-550. Beschikbaar vanaf, DOI: 10.1109/ISCAS.2017.8050369