Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

C. Zhang; L.J. Breems; G.I. Radulov; M. Bolatkale; Qilong Liu; J.A. Hegt; A.H.M. van Roermund

doi:10.1109/ISCAS.2017.8050369

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

C. Zhang, L.J. Breems, G.I. Radulov, M. Bolatkale, Qilong Liu, J.A. Hegt, A.H.M. van Roermund

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter is
not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz
MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

Originele taal-2	Engels
Titel	IEEE International Symposium on Circuits and Systems
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	547-550
Aantal pagina's	4
ISBN van elektronische versie	978-1-4673-6852-0
DOI's	https://doi.org/10.1109/ISCAS.2017.8050369
Status	Gepubliceerd - 29 mei 2017
Evenement	2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Baltimore, MD, USA, Baltimore, Verenigde Staten van Amerika Duur: 28 mei 2017 → 31 mei 2017 Congresnummer: 50

Congres

Congres	2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Verkorte titel	ISCAS 2017
Land/Regio	Verenigde Staten van Amerika
Stad	Baltimore
Periode	28/05/17 → 31/05/17

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Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A., & van Roermund, A. H. M. (2017). Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. In IEEE International Symposium on Circuits and Systems (blz. 547-550). Artikel 8050369 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2017.8050369

@inproceedings{84e558deeddf40a6829777a5982de1e7,

title = "Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs",

abstract = "This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.",

keywords = "Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC ",

author = "C. Zhang and L.J. Breems and G.I. Radulov and M. Bolatkale and Qilong Liu and J.A. Hegt and {van Roermund}, A.H.M.",

year = "2017",

month = may,

day = "29",

doi = "10.1109/ISCAS.2017.8050369",

language = "English",

pages = "547--550",

booktitle = "IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

}

Zhang, C, Breems, LJ , Radulov, GI, Bolatkale, M, Liu, Q, Hegt, JA & van Roermund, AHM 2017, Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. in IEEE International Symposium on Circuits and Systems., 8050369, Institute of Electrical and Electronics Engineers, Piscataway, blz. 547-550, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, Verenigde Staten van Amerika, 28/05/17. https://doi.org/10.1109/ISCAS.2017.8050369

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. / Zhang, C.; Breems, L.J.; Radulov, G.I. et al.
IEEE International Symposium on Circuits and Systems. Piscataway: Institute of Electrical and Electronics Engineers, 2017. blz. 547-550 8050369.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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T1 - Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

AU - Zhang, C.

AU - Breems, L.J.

AU - Radulov, G.I.

AU - Bolatkale, M.

AU - Liu, Qilong

AU - Hegt, J.A.

AU - van Roermund, A.H.M.

N1 - Conference code: 50

PY - 2017/5/29

Y1 - 2017/5/29

N2 - This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

AB - This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter isnot in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHzMASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

KW - Analog-to-Digital Converters, Sigma-Delta ADC, Excess Loop Delay Compensation, High-Speed ADC

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Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

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