Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

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This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter is
not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz
MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.
Originele taal-2Engels
TitelIEEE International Symposium on Circuits and Systems
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's547-550
Aantal pagina's4
ISBN van elektronische versie978-1-4673-6852-0
DOI's
StatusGepubliceerd - 29 mei 2017
Evenement50th IEEE International Symposium on Circuits and Systems (ISCAS 2017) - Baltimore, Verenigde Staten van Amerika
Duur: 28 mei 201731 mei 2017

Congres

Congres50th IEEE International Symposium on Circuits and Systems (ISCAS 2017)
Verkorte titelISCAS 2017
LandVerenigde Staten van Amerika
StadBaltimore
Periode28/05/1731/05/17

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Zhang, C., Breems, L. J., Radulov, G. I., Bolatkale, M., Liu, Q., Hegt, J. A., & van Roermund, A. H. M. (2017). Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. In IEEE International Symposium on Circuits and Systems (blz. 547-550). [8050369] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2017.8050369