Computing the entire area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator

M.R.C.M. Berkelaar, H.W. Buurman, J.A.G. Jess

Onderzoeksoutput: Bijdrage aan tijdschriftTijdschriftartikelAcademicpeer review

24 Citaten (Scopus)
113 Downloads (Pure)

Samenvatting

The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and/or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay tradeoff curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce tradeoff curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 two-level examples are given
Originele taal-2Engels
Pagina's (van-tot)1424-1434
Aantal pagina's11
TijdschriftIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume15
Nummer van het tijdschrift11
DOI's
StatusGepubliceerd - 1996

Vingerafdruk

Duik in de onderzoeksthema's van 'Computing the entire area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator'. Samen vormen ze een unieke vingerafdruk.

Citeer dit