Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

A. H. Montree, V. M.H. Meijssen, P. H. Woerlee

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

5 Citaten (Scopus)

Samenvatting

A low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n+-gate buried channel devices will be compared with the corresponding p+-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n+-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.

Originele taal-2Engels
Titel1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's11-14
Aantal pagina's4
ISBN van geprinte versie0780309782
DOI's
StatusGepubliceerd - 1 jan 1993
Extern gepubliceerdJa
Evenement1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
Duur: 12 mei 199314 mei 1993

Congres

Congres1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
Land/RegioTaiwan
StadTaipei
Periode12/05/9314/05/93

Vingerafdruk

Duik in de onderzoeksthema's van 'Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS'. Samen vormen ze een unieke vingerafdruk.

Citeer dit