@inbook{0e177e61b47e40f0b078deee203e2019,
title = "Comparison of an {\AE}thereal network on chip and traditional interconnects: two case studies",
abstract = "The growing complexity of multiprocessor systems on chip make the integration of Intellectual Property (IP) blocks into a working system a major challenge. Networks-on-Chip (NoCs) facilitate a modular design approach which addresses the hardware challenges in designing such a system. Guaranteed communication services, offered by the {\AE}thereal NoC, address the software challenges by making the system more robust and easier to design. This paper describes two existing bus-based reference designs and compares the original interconnects with an {\AE}thereal NoC. We show through these two case study implementations that the area cost of the NoC, which is dominated by the number of network connections, is competitive with traditional interconnects. Furthermore, we show that the latency in the NoC-based design is still acceptable for our application.",
author = "A.J.M. Moonen and C.L.L. Bartels and M.J.G. Bekooij and {Berg, van den}, R.M.J. and H. Bhullar and K.G.W. Goossens and P.R. Groeneveld and J. Huisken and {Meerbergen, van}, J.",
year = "2008",
doi = "10.1007/978-0-387-74909-9_18",
language = "English",
isbn = "978-0-387-74908-2",
series = "IFIP International Federation for Information Processing",
publisher = "Springer",
pages = "317--336",
editor = "{De Micheli}, G. and S. Mir and R. Reis",
booktitle = "VLSI-SoC: research trends in VLSI and systems on chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006), October 16 - 18, 2006, Nice, France",
address = "Germany",
}