Comparative Analysis of Short-Circuit Behavior and Failure Mechanisms in Planar and Trench-Gate SiC MOSFETs

Silicon carbide (SiC) MOSFETs have been widely adopted in power electronics applications. However, their robustness, particularly short-circuit robustness—remains a critical limitation.
This work investigates the short-circuit characteristics of two SiC MOSFETs with planar-gate and trench-gate structures.
Experimental results showed that both devices exhibited gatevoltage drop during short-circuit events, with a more pronounced voltage drop (3.8 V) observed in the planar-gate device. During the turn-off phase, the planar-gate MOSFET also showed a larger drain current tail compared to its trench-gate counterpart. In addition, both devices experienced delayed gate failure after shortcircuit operation. By employing calibrated TCAD simulations, the influence of Fowler–Nordheim (FN) tunneling current and hotcarrier injection current on the gate-voltage drop was analyzed.
The theoretical relationship between the drain current tail, the junction temperature and the applied voltage was derived, which explained the observed difference between the two device structures.
Finally, thermomechanical stress analysis during the short circuit operation revealed the evolution of aluminum layer and the fracture mechanism of the interlayer dielectric (ILD) above the gate. These phenomena led to the formation of conductive paths, which were identified as the root cause of delayed gate failure. Analysis of failed devices using OBIRCH (Optical Beam Induced Resistance Change), FIB (Focused ion beam), and EDS (Energy-dispersive X-ray spectroscopy) confirmed the presence of melted aluminum and conductive channels within the ILD, validating the failure mechanism.