Checking and deriving module paths in Verilog cell library descriptions

M. Raffelsieper, M.R. Mousavi, C. Strolenberg

    Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

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    Samenvatting

    Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Specifying such paths manually is an error prone task; a forgotten path is interpreted as a zero delay, which can cause further flaws in the subsequent design steps. Moreover, one can specify superfluous module paths, i.e., module paths that can never occur in any practical run of the model and hence, make excessive restrictions on the subsequent design decision. This paper presents a method to check whether the given module paths are reflected in the functional implementation. Complementing this check, we also present a method to derive module paths from a functional description of a cell.
    Originele taal-2Engels
    TitelDesign, Automation and Test in Europe Conference & Exhibition 2010 (DATE'10, Dresden, Germany, March 8-12, 2010)
    UitgeverijInstitute of Electrical and Electronics Engineers
    Pagina's1506-1511
    ISBN van geprinte versie978-398108016-2
    StatusGepubliceerd - 2010

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