Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access

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34 Citaten (Scopus)
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Samenvatting

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.
Originele taal-2Engels
Titel2010 IEEE Asia Pacific Conference on Circuits and Systems
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's544-547
Aantal pagina's4
ISBN van elektronische versie978-1-4244-7456-1
ISBN van geprinte versie978-1-4244-7454-7
DOI's
StatusGepubliceerd - dec 2010
Extern gepubliceerdJa
Evenement2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010) - Kuala Lumpur, Maleisië
Duur: 6 dec 20109 dec 2010

Congres

Congres2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
Verkorte titelAPCCAS 2010
Land/RegioMaleisië
StadKuala Lumpur
Periode6/12/109/12/10

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