BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching

R. Jordans; E. Diken; L. Jozwiak; H. Corporaal

doi:10.1109/DDECS.2014.6868768

BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching

R. Jordans, E. Diken, L. Jozwiak, H. Corporaal

Electronic Systems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

2 Citaten (Scopus)

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In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.

Originele taal-2	Engels
Titel	Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	83-88
ISBN van geprinte versie	978-1-4799-4560-3
DOI's	https://doi.org/10.1109/DDECS.2014.6868768
Status	Gepubliceerd - 2014
Evenement	conference; DDECS'14; 2014-04-23; 2014-04-25 - Duur: 23 apr. 2014 → 25 apr. 2014

Congres

Congres	conference; DDECS'14; 2014-04-23; 2014-04-25
Periode	23/04/14 → 25/04/14
Ander	DDECS'14

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10.1109/DDECS.2014.6868768

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Jordans, R., Diken, E., Jozwiak, L., & Corporaal, H. (2014). BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. In Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland (blz. 83-88). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/DDECS.2014.6868768

Jordans, R. ; Diken, E. ; Jozwiak, L. et al. / BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway : Institute of Electrical and Electronics Engineers, 2014. blz. 83-88

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title = "BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching",

abstract = "In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.",

author = "R. Jordans and E. Diken and L. Jozwiak and H. Corporaal",

year = "2014",

doi = "10.1109/DDECS.2014.6868768",

language = "English",

isbn = "978-1-4799-4560-3",

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publisher = "Institute of Electrical and Electronics Engineers",

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note = "conference; DDECS'14; 2014-04-23; 2014-04-25 ; Conference date: 23-04-2014 Through 25-04-2014",

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Jordans, R, Diken, E, Jozwiak, L & Corporaal, H 2014, BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. in Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Institute of Electrical and Electronics Engineers, Piscataway, blz. 83-88, conference; DDECS'14; 2014-04-23; 2014-04-25, 23/04/14. https://doi.org/10.1109/DDECS.2014.6868768

BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. / Jordans, R.; Diken, E.; Jozwiak, L. et al.
Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway: Institute of Electrical and Electronics Engineers, 2014. blz. 83-88.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AB - In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.

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BT - Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland

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Jordans R, Diken E, Jozwiak L, Corporaal H. BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. In Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway: Institute of Electrical and Electronics Engineers. 2014. blz. 83-88 doi: 10.1109/DDECS.2014.6868768

BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching

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