Samenvatting
Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its test set, and maximal bandwidth that the functional interconnect can offer between ATE and module-under-test, our approach designs a test wrapper for the module-under-test such that the test length is minimized. Unfortunately, it is unavoidable that with the test data also unused (idle) bits are transported. This paper presents a TAM bandwidth utilization analysis and techniques for idle bits reduction, to minimize the test length. We classify the idle bits into four types which explain the reason for bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits. © 2008 IEEE.
Originele taal-2 | Engels |
---|---|
Titel | 2008 13th European Test Symposium |
Plaats van productie | Piscataway |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Pagina's | 21-26 |
Aantal pagina's | 6 |
ISBN van geprinte versie | 978-0-7695-3150-2 |
DOI's | |
Status | Gepubliceerd - 2008 |
Evenement | 13th IEEE European Test Symposium (ETS 2008) - Verbania, Italië Duur: 25 mei 2008 → 29 mei 2008 |
Congres
Congres | 13th IEEE European Test Symposium (ETS 2008) |
---|---|
Land/Regio | Italië |
Stad | Verbania |
Periode | 25/05/08 → 29/05/08 |