Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms

Hugo de Man, Francky Catthoor, Gert Goossens, Jan Vanhoof, Jef van Meerbergen, Stefaan Note, Jos Huisken

Onderzoeksoutput: Bijdrage aan tijdschriftTijdschriftartikelpeer review

67 Citaten (Scopus)


Digital signal processing (DSP) is a rapidly growing discipline as VLSI technology makes real-time digital algorithms for speech, audio, image processing, video, and control systems economically feasible. Due to the competitiveness of the application field, cutting design time is a key issue for DSP. Silicon compilation is a way to achieve this. In this paper the state of the art of compiling DSP algorithms into silicon is discussed. First it is indicated how digital signal processing differs from numerical data processing, including the consequences on the synthesis tools. Unlike compilers generating general-purpose microprocessors, DSP synthesis requires tools for analysis, optimization and simulation of the bit-true behavior of the algorithm at the highest level. An applicative input language for specifying the behavior of DSP systems is advocated. Based on a wide span of DSP applications, four classes of architectures are distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioural DSP specification. The four selected architectural styles are best characterized by the following keywords: hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths and, finally, regular arrays. Each of the Cathedral compilers is based on a mixture of knowledge-based architecture generation techniques and algorithmic optimizations. Silicon is generated from technology-updatable libraries of primitive cells, by means of structured module-generators or by using a standard-cell design system. Attention is paid to the assembly of test patterns for the synthesized chips. The Cathedral programs support interactive synthesis for the four above-mentioned architectures, all the way from the applicative bit-true specification to silicon. For each compiler the design trajectory starting from a high-level specification down to layout is analyzed in the paper. Each of the Cathedrals and their underlying methodology is illustrated with the complete design of a representative example.

Originele taal-2Engels
Pagina's (van-tot)319-335
Aantal pagina's17
TijdschriftProceedings of the IEEE
Nummer van het tijdschrift2
StatusGepubliceerd - 1 jan 1990
Extern gepubliceerdJa


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