Approaches and opportunities for area-selective atomic layer deposition

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Citaties (Scopus)
1 Downloads (Pure)

Uittreksel

With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.

Originele taal-2Engels
Titel2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's2
ISBN van elektronische versie9781538648254
DOI's
StatusGepubliceerd - 3 jul 2018
Evenement2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018 - Hsinchu, Taiwan
Duur: 16 apr 201819 apr 2018

Congres

Congres2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
LandTaiwan
StadHsinchu
Periode16/04/1819/04/18

Vingerafdruk

Atomic layer deposition
atomic layer epitaxy
Fabrication
fabrication
Processing
alignment
Semiconductor materials

Citeer dit

Mackus, A. J. M. (2018). Approaches and opportunities for area-selective atomic layer deposition. In 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018 [8403864] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSI-TSA.2018.8403864
Mackus, Adriaan J.M. / Approaches and opportunities for area-selective atomic layer deposition. 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018. Piscataway : Institute of Electrical and Electronics Engineers, 2018.
@inproceedings{dbfffc34e0fe4cabb04f3a6ccf52435d,
title = "Approaches and opportunities for area-selective atomic layer deposition",
abstract = "With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.",
author = "Mackus, {Adriaan J.M.}",
year = "2018",
month = "7",
day = "3",
doi = "10.1109/VLSI-TSA.2018.8403864",
language = "English",
booktitle = "2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Mackus, AJM 2018, Approaches and opportunities for area-selective atomic layer deposition. in 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018., 8403864, Institute of Electrical and Electronics Engineers, Piscataway, 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018, Hsinchu, Taiwan, 16/04/18. https://doi.org/10.1109/VLSI-TSA.2018.8403864

Approaches and opportunities for area-selective atomic layer deposition. / Mackus, Adriaan J.M.

2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8403864.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

TY - GEN

T1 - Approaches and opportunities for area-selective atomic layer deposition

AU - Mackus, Adriaan J.M.

PY - 2018/7/3

Y1 - 2018/7/3

N2 - With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.

AB - With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.

UR - http://www.scopus.com/inward/record.url?scp=85050508662&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2018.8403864

DO - 10.1109/VLSI-TSA.2018.8403864

M3 - Conference contribution

AN - SCOPUS:85050508662

BT - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Mackus AJM. Approaches and opportunities for area-selective atomic layer deposition. In 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018. Piscataway: Institute of Electrical and Electronics Engineers. 2018. 8403864 https://doi.org/10.1109/VLSI-TSA.2018.8403864