An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

P. Kaul; H. Gao; Xin He; P.G.M. Baltus

doi:10.1109/ISCAS.2018.8350984

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

P. Kaul
, H. Gao
, Xin He
, P.G.M. Baltus

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

Originele taal-2	Engels
Titel	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	5
ISBN van elektronische versie	978-1-5386-4881-0
ISBN van geprinte versie	978-1-5386-4882-7
DOI's	https://doi.org/10.1109/ISCAS.2018.8350984
Status	Gepubliceerd - 26 apr. 2018
Evenement	2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) - Florence Conference Center, Florence, Italië Duur: 27 mei 2018 → 30 mei 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Congres

Congres	2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)
Verkorte titel	ISCAS 2018
Land/Regio	Italië
Stad	Florence
Periode	27/05/18 → 30/05/18
Internet adres	https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

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@inproceedings{ae77454fa41c4763ac411c96b10b2c06,

title = "An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers",

abstract = "This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40\% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.",

keywords = "Delay locked loop, Quadrature voltage controlled oscillator, Voltage controlled delay line, UWB, low phase noise, low power",

author = "P. Kaul and H. Gao and Xin He and P.G.M. Baltus",

year = "2018",

month = apr,

day = "26",

doi = "10.1109/ISCAS.2018.8350984",

language = "English",

isbn = "978-1-5386-4882-7",

booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

url = "https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884",

}

Kaul, P, Gao, H, He, X & Baltus, PGM 2018, An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8350984, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italië, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8350984

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers. / Kaul, P.; Gao, H.; He, Xin et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2018. 8350984.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

AU - Kaul, P.

AU - Gao, H.

AU - He, Xin

AU - Baltus, P.G.M.

PY - 2018/4/26

Y1 - 2018/4/26

N2 - This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

AB - This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

KW - Delay locked loop

KW - Quadrature voltage controlled oscillator

KW - Voltage controlled delay line

KW - UWB

KW - low phase noise

KW - low power

UR - https://www.scopus.com/pages/publications/85057074982

U2 - 10.1109/ISCAS.2018.8350984

DO - 10.1109/ISCAS.2018.8350984

M3 - Conference contribution

AN - SCOPUS:85057074982

SN - 978-1-5386-4882-7

BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)

Y2 - 27 May 2018 through 30 May 2018

ER -

An UWB, low-noise, low-power quadrature VCO using delay-locked loop in 40-nm CMOS for image-rejection receivers

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