An ultra-low power 1.7-2.7 GHz fractional-N sub-sampling digital frequency synthesizer and modulator for IoT applications in 40 nm CMOS

Yao Hong Liu, Johan van den Heuvel, Takashi Kuramochi, Benjamin Busze, Paul Mateman, Vamshi Krishna Chillara, Bindi Wang, Robert Bogdan Staszewski, Kathleen Philips

Onderzoeksoutput: Bijdrage aan tijdschriftTijdschriftartikelAcademicpeer review

21 Citaten (Scopus)


This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a "variable-preconditioned LMS" calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.

Originele taal-2Engels
Pagina's (van-tot)1094-1105
Aantal pagina's12
TijdschriftIEEE Transactions on Circuits and Systems I: Regular Papers
Nummer van het tijdschrift5
StatusGepubliceerd - 1 mei 2017


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