An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Boyu Hu; Yuan Du; Rulin Huang; Jeffrey Lee; Young-Kai Chen; Mau-Chung Frank Chang

doi:10.1109/TVLSI.2017.2737523

An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Boyu Hu, Yuan Du, Rulin Huang, Jeffrey Lee, Young-Kai Chen, Mau-Chung Frank Chang

Onderzoeksoutput: Bijdrage aan tijdschrift › Tijdschriftartikel › Academic › peer review

5 Citaten (Scopus)

Samenvatting

This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

Originele taal-2	Engels
Artikelnummer	8012497
Pagina's (van-tot)	3260-3264
Aantal pagina's	5
Tijdschrift	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	25
Nummer van het tijdschrift	11
DOI's	https://doi.org/10.1109/TVLSI.2017.2737523
Status	Gepubliceerd - nov. 2017
Extern gepubliceerd	Ja

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© 2017 IEEE.

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abstract = "This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.",

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author = "Boyu Hu and Yuan Du and Rulin Huang and Jeffrey Lee and Young-Kai Chen and Chang, {Mau-Chung Frank}",

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An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

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