An improved algorithm for slot selection in the AEthereal network-on-chip

R.A. Stefan, K.G.W. Goossens

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

4 Citaten (Scopus)


The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.
Originele taal-2Engels
TitelProceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece
UitgeverijAssociation for Computing Machinery, Inc
ISBN van geprinte versie978-1-4503-0272-2
StatusGepubliceerd - 2011
Evenementconference; INA-OMC 2011; 2011-01-23; 2011-01-23 -
Duur: 23 jan. 201123 jan. 2011


Congresconference; INA-OMC 2011; 2011-01-23; 2011-01-23
AnderINA-OMC 2011


Duik in de onderzoeksthema's van 'An improved algorithm for slot selection in the AEthereal network-on-chip'. Samen vormen ze een unieke vingerafdruk.

Citeer dit