An improved algorithm for slot selection in the AEthereal network-on-chip

R.A. Stefan; K.G.W. Goossens

doi:10.1145/1930037.1930040

An improved algorithm for slot selection in the AEthereal network-on-chip

R.A. Stefan, K.G.W. Goossens

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

4 Citaten (Scopus)

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The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.

Originele taal-2	Engels
Titel	Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece
Uitgeverij	Association for Computing Machinery, Inc
Pagina's	7-10
ISBN van geprinte versie	978-1-4503-0272-2
DOI's	https://doi.org/10.1145/1930037.1930040
Status	Gepubliceerd - 2011
Evenement	conference; INA-OMC 2011; 2011-01-23; 2011-01-23 - Duur: 23 jan. 2011 → 23 jan. 2011

Congres

Congres	conference; INA-OMC 2011; 2011-01-23; 2011-01-23
Periode	23/01/11 → 23/01/11
Ander	INA-OMC 2011

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Stefan, R. A., & Goossens, K. G. W. (2011). An improved algorithm for slot selection in the AEthereal network-on-chip. In Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece (blz. 7-10). Association for Computing Machinery, Inc. https://doi.org/10.1145/1930037.1930040

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abstract = "The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.",

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note = "conference; INA-OMC 2011; 2011-01-23; 2011-01-23 ; Conference date: 23-01-2011 Through 23-01-2011",

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Stefan, RA & Goossens, KGW 2011, An improved algorithm for slot selection in the AEthereal network-on-chip. in Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece. Association for Computing Machinery, Inc, blz. 7-10, conference; INA-OMC 2011; 2011-01-23; 2011-01-23, 23/01/11. https://doi.org/10.1145/1930037.1930040

An improved algorithm for slot selection in the AEthereal network-on-chip. / Stefan, R.A.; Goossens, K.G.W.

Proceedings of the 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2011), 23 January 2011, Heraklion, Greece. Association for Computing Machinery, Inc, 2011. blz. 7-10.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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N2 - The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.

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ER -

An improved algorithm for slot selection in the AEthereal network-on-chip

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