An exercise in the automatic verification of asynchronous designs

A.M. Bailey, G.A. McCaskill, G.J. Milne

Onderzoeksoutput: Bijdrage aan tijdschriftTijdschriftartikelAcademicpeer review

13 Citaten (Scopus)


This paper illustrates the practical application of an automatic formal verification technique to circuit designs of realistic complexity. The Circal System is presented and a number of asynchronous hardware modules are described and formally verified using it. Asynchronous logic is generally considered hard to design and analyse, and this serves as an appropriate demonstration of the features of a formal description and verification system.
Originele taal-2Engels
Pagina's (van-tot)213-242
TijdschriftFormal Methods in System Design
Nummer van het tijdschrift3
StatusGepubliceerd - 1994

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