An exercise in the automatic verification of asynchronous designs

A.M. Bailey; G.A. McCaskill; G.J. Milne

doi:10.1007/BF01384047

An exercise in the automatic verification of asynchronous designs

A.M. Bailey, G.A. McCaskill, G.J. Milne

Department of Mathematics and Computer Science

Onderzoeksoutput: Bijdrage aan tijdschrift › Tijdschriftartikel › Academic › peer review

13 Citaten (Scopus)

Samenvatting

This paper illustrates the practical application of an automatic formal verification technique to circuit designs of realistic complexity. The Circal System is presented and a number of asynchronous hardware modules are described and formally verified using it. Asynchronous logic is generally considered hard to design and analyse, and this serves as an appropriate demonstration of the features of a formal description and verification system.

Originele taal-2	Engels
Pagina's (van-tot)	213-242
Tijdschrift	Formal Methods in System Design
Volume	4
Nummer van het tijdschrift	3
DOI's	https://doi.org/10.1007/BF01384047
Status	Gepubliceerd - 1994

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