An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Y. V. Ponomarev, P. A. Stolk, A. C.M.C. van Brandenburg, C. J.J. Dachs, M. Kaiser, A. H. Montree, R. Roes, J. Schmitz, P. H. Woerlee

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

4 Citaten (Scopus)

Samenvatting

An aggressive lateral MOS channel profiling combined with gate workfunction engineering for sub-0.13μm generation PMOSFETs oriented for low-voltage operations was studied. In this scheme, the Ge fraction in poly-SiGe gate was used to control VT, while short channel effects (SCEs) were completely suppressed down to 100nm gate lengths by heavily-doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no VT roll-off behavior, and 67mV/dec sub-VT voltage swing. Process variation analysis confirmed the high manufacturing potential for the approach suggested.

Originele taal-2Engels
Titel1999 Symposium on VLSI Technology. Digest of Technical Papers
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's65-66
Aantal pagina's2
ISBN van geprinte versie4-930813-93-X
DOI's
StatusGepubliceerd - 1 dec 1999
Extern gepubliceerdJa
Evenement1999 Symposium on VLSI Technology - Kyoto, Jpn
Duur: 14 jun 199916 jun 1999

Congres

Congres1999 Symposium on VLSI Technology
StadKyoto, Jpn
Periode14/06/9916/06/99

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