An efficient CMOS bridging fault simulator with SPICE accuracy

C. Di, J.A.G. Jess

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11 Citaten (Scopus)
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Samenvatting

This paper presents an alternative modeling and simulation method for CMOS bridging faults. The significance of the method is the introduction of a set of generic-bridge tables which characterize the bridged outputs for each bridge and a set of generic-cell tables which characterize how each cell propagates a logically undefined input. These two sets of tables are derived dynamically for a specific design by using a SPICE circuit simulator. Then they can be used by any logic fault simulator to simulate bridging faults. In this way, the proposed method can perform very fast bridging fault simulation yet with SPICE accuracy. The paper shows how these two sets of tables are derived and used in a parallel pattern fault simulator. Experimental results on ISCAS85 benchmarks are promising
Originele taal-2Engels
Pagina's (van-tot)1071-1080
Aantal pagina's11
TijdschriftIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume15
Nummer van het tijdschrift9
DOI's
StatusGepubliceerd - 1996

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