An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f T SiGe BiCMOS technology

D. Smola; J. H. Huijsing; K. A.A. Makinwa; H. V.D. Ploeg; M. Vertregt; L. Breems

doi:10.1109/ESSCIR.2006.307617

An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f _T SiGe BiCMOS technology

D. Smola
, J. H. Huijsing
, K. A.A. Makinwa
, H. V.D. Ploeg
, M. Vertregt
, L. Breems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

6 Citaten (Scopus)

Samenvatting

In this paper we present design and measurements of a high-speed track-and-hold (T&H) circuit. The circuit was implemented in a low-cost 67GHzf _r SiGe technology. At 4GS/s the circuit achieves SNR better than 52dB and THD of -50.5dB, corresponding to 8.1 effective bits. This performance is achieved for input frequencies up to 1.1GHz with a differential full-scale input swing of 0.9V _PP. The power dissipation of the T&H, including buffers and clock driver, is 590mW. Since measurements at such high frequencies are challenging, a full description of the measurement setup is provided.

Originele taal-2	Engels
Titel	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	408-411
Aantal pagina's	4
ISBN van geprinte versie	1-4244-0302-2, 1-4244-0303-0
DOI's	https://doi.org/10.1109/ESSCIR.2006.307617
Status	Gepubliceerd - 1 dec. 2006
Extern gepubliceerd	Ja
Evenement	32nd European Solid State Circuits Conference (ESSCIRC 2006) - Montreux, Zwitserland Duur: 19 sep. 2006 → 21 sep. 2006 Congresnummer: 32

Congres

Congres	32nd European Solid State Circuits Conference (ESSCIRC 2006)
Verkorte titel	ESSCIRC 2006
Land/Regio	Zwitserland
Stad	Montreux
Periode	19/09/06 → 21/09/06

Toegang tot document

10.1109/ESSCIR.2006.307617

Andere bestanden en links

Link to publication in Scopus

Citeer dit

Smola, D., Huijsing, J. H., Makinwa, K. A. A., Ploeg, H. V. D., Vertregt, M., & Breems, L. (2006). An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f _T SiGe BiCMOS technology. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (blz. 408-411). Artikel 4099790 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIR.2006.307617

@inproceedings{deeb2dc17aed466a9112705ee12b72f1,

title = "An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f T SiGe BiCMOS technology",

abstract = "In this paper we present design and measurements of a high-speed track-and-hold (T\&H) circuit. The circuit was implemented in a low-cost 67GHzf r SiGe technology. At 4GS/s the circuit achieves SNR better than 52dB and THD of -50.5dB, corresponding to 8.1 effective bits. This performance is achieved for input frequencies up to 1.1GHz with a differential full-scale input swing of 0.9V PP. The power dissipation of the T\&H, including buffers and clock driver, is 590mW. Since measurements at such high frequencies are challenging, a full description of the measurement setup is provided.",

author = "D. Smola and Huijsing, \{J. H.\} and Makinwa, \{K. A.A.\} and Ploeg, \{H. V.D.\} and M. Vertregt and L. Breems",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ESSCIR.2006.307617",

language = "English",

isbn = "1-4244-0302-2",

pages = "408--411",

booktitle = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "32nd European Solid State Circuits Conference (ESSCIRC 2006), ESSCIRC 2006 ; Conference date: 19-09-2006 Through 21-09-2006",

}

Smola, D, Huijsing, JH, Makinwa, KAA, Ploeg, HVD, Vertregt, M & Breems, L 2006, An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f _T SiGe BiCMOS technology. in ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference., 4099790, Institute of Electrical and Electronics Engineers, Piscataway, blz. 408-411, 32nd European Solid State Circuits Conference (ESSCIRC 2006), Montreux, Zwitserland, 19/09/06. https://doi.org/10.1109/ESSCIR.2006.307617

An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f _T SiGe BiCMOS technology. / Smola, D.; Huijsing, J. H.; Makinwa, K. A.A. et al.
ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. Piscataway: Institute of Electrical and Electronics Engineers, 2006. blz. 408-411 4099790.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - An 8-bit, 4-Gsample/s track-and-hold in a 67GHz f T SiGe BiCMOS technology

AU - Smola, D.

AU - Huijsing, J. H.

AU - Makinwa, K. A.A.

AU - Ploeg, H. V.D.

AU - Vertregt, M.

AU - Breems, L.

N1 - Conference code: 32

PY - 2006/12/1

Y1 - 2006/12/1

N2 - In this paper we present design and measurements of a high-speed track-and-hold (T&H) circuit. The circuit was implemented in a low-cost 67GHzf r SiGe technology. At 4GS/s the circuit achieves SNR better than 52dB and THD of -50.5dB, corresponding to 8.1 effective bits. This performance is achieved for input frequencies up to 1.1GHz with a differential full-scale input swing of 0.9V PP. The power dissipation of the T&H, including buffers and clock driver, is 590mW. Since measurements at such high frequencies are challenging, a full description of the measurement setup is provided.

AB - In this paper we present design and measurements of a high-speed track-and-hold (T&H) circuit. The circuit was implemented in a low-cost 67GHzf r SiGe technology. At 4GS/s the circuit achieves SNR better than 52dB and THD of -50.5dB, corresponding to 8.1 effective bits. This performance is achieved for input frequencies up to 1.1GHz with a differential full-scale input swing of 0.9V PP. The power dissipation of the T&H, including buffers and clock driver, is 590mW. Since measurements at such high frequencies are challenging, a full description of the measurement setup is provided.

UR - https://www.scopus.com/pages/publications/50649110316

U2 - 10.1109/ESSCIR.2006.307617

DO - 10.1109/ESSCIR.2006.307617

M3 - Conference contribution

AN - SCOPUS:50649110316

SN - 1-4244-0302-2

SN - 1-4244-0303-0

SP - 408

EP - 411

BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 32nd European Solid State Circuits Conference (ESSCIRC 2006)

Y2 - 19 September 2006 through 21 September 2006

ER -