An interactive cnvironmenl for the analysis of yield infonmation necded on modem integratcd circuit manufacturing lines is prcsented. The system is ahlc to quantify wafer yiclds, yield variations betwccn wafers and within the wafers themselves, yields of wafer hatchcs, yield variations between batclles, to idemify clusters in wafers and or in lots, and is also able to predict wafer yields via simple simulation tools. The analysis technique investigates the effect of correlated and uncorrelated sourccs of yield loss. Such infonmation can be used to study the changes in thc technological proccss. Graphical displays in the fonn of wafer maps arc used to represent the spatial distrihution of dice in the wafer. Facilities such as radial and angular distribution analyses, among others, arc provided to examine data, and hypothetical wafer maps arc created to visualise and predict simulated wafer yields.
|Naam||EUT Technical Report|