Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer.

A. Beric, G. Haan, de, R. Sethuraman, J. Meerbergen, van

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Citaten (Scopus)

Samenvatting

De-interlacing is a major determinant of image quality in a modern display processing chain. The de-interlacing method based on the generalized sampling theorem (GST)applied to motion estimation and motion compensation provides the best de-interlacing results. With HDTV interlaced input material (1920*1080i), this method requires about 1000 GOPs and a communication bandwidth around 10 Gbytes/sec. We analyze and simplify the algorithm and propose a processing architecture. As a result, the operation count of the motion estimator decreases with a factor of 5.5 and the bandwidth to local pixel storage with a factor of 3.3 with only mild and acceptable quality loss. We present a task breakup and a suitable heterogeneous multi-processor architecture. The task break-up is such that the computational load of the processors is balanced and the flexibility of the architecture is preserved within the application domain. To cope with the large memory bandwidth requirements, we exploit locality of reference with multi-level scratchpad memories.
Originele taal-2Engels
TitelProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan
Plaats van productiePiscataway, New Jersey, USA
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's2943-2946
ISBN van geprinte versie0-7803-8834-8
StatusGepubliceerd - 2005
Evenement2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005) - Kobe, Japan
Duur: 23 mei 200526 mei 2005

Congres

Congres2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)
Verkorte titelISCAS 2005
Land/RegioJapan
StadKobe
Periode23/05/0526/05/05
AnderIEEE International Symposium on Circuits and Systems 2005

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