Algorithm parallelism estimation for constraining instruction-set synthesis for VLIW processors

R. Jordans; R. Corvino; L. Jozwiak

doi:10.1109/DSD.2012.21

Algorithm parallelism estimation for constraining instruction-set synthesis for VLIW processors

R. Jordans, R. Corvino, L. Jozwiak

Electronic Systems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

4 Citaten (Scopus)

1 Downloads (Pure)

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Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. This paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application. We explain important reasons for computing and using such parallelism bounds, discuss the implementation of several methods, and our experimental research performed to evaluate the efficiency of each method

Originele taal-2	Engels
Titel	Proceedings of the 15th Euromicro Conference on Digital System Design (DSD'12), 5-8 September 2012, Cesme, Izmir, Turkey
Plaats van productie	Brussels
Uitgeverij	IEEE Computer Society
Pagina's	152-155
ISBN van geprinte versie	978-1-4673-2498-4
DOI's	https://doi.org/10.1109/DSD.2012.21
Status	Gepubliceerd - 2012
Evenement	15th Euromicro Conference on Digital System Design (DSD 2012) - Çeşme, Turkije Duur: 5 sep. 2012 → 8 sep. 2012 Congresnummer: 15 http://www.univ-valenciennes.fr/congres/dsd2012/

Congres

Congres	15th Euromicro Conference on Digital System Design (DSD 2012)
Verkorte titel	DSD 2012
Land/Regio	Turkije
Stad	Çeşme
Periode	5/09/12 → 8/09/12
Ander	DSD'12
Internet adres	http://www.univ-valenciennes.fr/congres/dsd2012/

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10.1109/DSD.2012.21

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@inproceedings{df50db401ddd41268c8c7ef8fa472d83,

title = "Algorithm parallelism estimation for constraining instruction-set synthesis for VLIW processors",

abstract = "Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. This paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application. We explain important reasons for computing and using such parallelism bounds, discuss the implementation of several methods, and our experimental research performed to evaluate the efficiency of each method",

author = "R. Jordans and R. Corvino and L. Jozwiak",

year = "2012",

doi = "10.1109/DSD.2012.21",

language = "English",

isbn = "978-1-4673-2498-4",

pages = "152--155",

booktitle = "Proceedings of the 15th Euromicro Conference on Digital System Design (DSD'12), 5-8 September 2012, Cesme, Izmir, Turkey",

publisher = "IEEE Computer Society",

address = "United States",

note = "15th Euromicro Conference on Digital System Design (DSD 2012), DSD 2012 ; Conference date: 05-09-2012 Through 08-09-2012",

url = "http://www.univ-valenciennes.fr/congres/dsd2012/",

}

Jordans, R, Corvino, R & Jozwiak, L 2012, Algorithm parallelism estimation for constraining instruction-set synthesis for VLIW processors. in Proceedings of the 15th Euromicro Conference on Digital System Design (DSD'12), 5-8 September 2012, Cesme, Izmir, Turkey. IEEE Computer Society, Brussels, blz. 152-155, 15th Euromicro Conference on Digital System Design (DSD 2012), Çeşme, Turkije, 5/09/12. https://doi.org/10.1109/DSD.2012.21

Algorithm parallelism estimation for constraining instruction-set synthesis for VLIW processors. / Jordans, R.; Corvino, R.; Jozwiak, L.
Proceedings of the 15th Euromicro Conference on Digital System Design (DSD'12), 5-8 September 2012, Cesme, Izmir, Turkey. Brussels: IEEE Computer Society, 2012. blz. 152-155.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AU - Jozwiak, L.

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N2 - Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. This paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application. We explain important reasons for computing and using such parallelism bounds, discuss the implementation of several methods, and our experimental research performed to evaluate the efficiency of each method

AB - Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. This paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application. We explain important reasons for computing and using such parallelism bounds, discuss the implementation of several methods, and our experimental research performed to evaluate the efficiency of each method

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DO - 10.1109/DSD.2012.21

M3 - Conference contribution

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Algorithm parallelism estimation for constraining instruction-set synthesis for VLIW processors

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