Accelerating time domain simulations of PLLs

G. De Luca, W.H.A. Schilders, P. Bolcato, R. Larcheveque, J. Rommes

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

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Samenvatting

We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and the loop divider.

Originele taal-2Engels
Titel2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's4
ISBN van elektronische versie9781509003495
DOI's
StatusGepubliceerd - 20 jun 2016
Evenement20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy - Turin, Italië
Duur: 8 mei 201611 mei 2016
http://www.spi2016.org/

Congres

Congres20th IEEE Workshop on Signal and Power Integrity (SPI 2016), 8-11 May 2016, Turin, Italy
Verkorte titelSPI 2016
LandItalië
StadTurin
Periode8/05/1611/05/16
Internet adres

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