A wideband RF mixing-DAC achieving IMD<-82 dBc up to 1.9 GHz

E. Bechthum, G.I. Radulov, J. Briaire, G.J.G.M. Geelen, A.H.M. van Roermund

Onderzoeksoutput: Bijdrage aan tijdschriftTijdschriftartikelAcademicpeer review

14 Citaties (Scopus)

Uittreksel

This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD<−82 dBc up to 1.9 GHz and output noise lower than –165 dBm/Hz.
TaalEngels
Pagina's1374-1384
Aantal pagina's11
TijdschriftIEEE Journal of Solid-State Circuits
Volume51
Nummer van het tijdschrift6
DOI's
StatusGepubliceerd - 16 mei 2016

Vingerafdruk

Calibration
Digital signal processing
Synchronization
Hardware

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    Bechthum, E. ; Radulov, G.I. ; Briaire, J. ; Geelen, G.J.G.M. ; van Roermund, A.H.M./ A wideband RF mixing-DAC achieving IMD<-82 dBc up to 1.9 GHz. In: IEEE Journal of Solid-State Circuits. 2016 ; Vol. 51, Nr. 6. blz. 1374-1384
    @article{b46a0fc41f784af09c1d4867e88e1c6d,
    title = "A wideband RF mixing-DAC achieving IMD<-82 dBc up to 1.9 GHz",
    abstract = "This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD<−82 dBc up to 1.9 GHz and output noise lower than –165 dBm/Hz.",
    keywords = "Current-steering DAC, high linearity, LTE, mixing-DAC, multi-standard, multicarrier GSM, RF DAC, WCDMA.",
    author = "E. Bechthum and G.I. Radulov and J. Briaire and G.J.G.M. Geelen and {van Roermund}, A.H.M.",
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    A wideband RF mixing-DAC achieving IMD<-82 dBc up to 1.9 GHz. / Bechthum, E.; Radulov, G.I.; Briaire, J.; Geelen, G.J.G.M.; van Roermund, A.H.M.

    In: IEEE Journal of Solid-State Circuits, Vol. 51, Nr. 6, 16.05.2016, blz. 1374-1384.

    Onderzoeksoutput: Bijdrage aan tijdschriftTijdschriftartikelAcademicpeer review

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    AU - Bechthum,E.

    AU - Radulov,G.I.

    AU - Briaire,J.

    AU - Geelen,G.J.G.M.

    AU - van Roermund,A.H.M.

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    N2 - This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD<−82 dBc up to 1.9 GHz and output noise lower than –165 dBm/Hz.

    AB - This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD<−82 dBc up to 1.9 GHz and output noise lower than –165 dBm/Hz.

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