Samenvatting
This paper presents a latched comparator designed in a double-gate p-type-only organic thin film transistors (OTFTs) technology. The circuit is tailored to take the maximum advantage of the features of the double-gate technology, which allows an input capacitance of only ~35fF. The measured single stage-latch reaches rail-to-rail logic levels with less than 100mV differential input signal and about 10V input common mode range for VDD=20V. The DC small-signal gain is larger than 46dB and the static power dissipation is ~30nW. All measurements were taken in air and in daylight.
Originele taal-2 | Engels |
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Titel | Proceedings of the 38th European Solid-State Circuits Conference (ESSCIRC '12), 17-21 September 2012, Bordeaux, France |
Plaats van productie | Piscataway |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Pagina's | 141-144 |
ISBN van geprinte versie | 978-1-4673-3085-5 |
DOI's | |
Status | Gepubliceerd - 2012 |
Evenement | 2012 Proceedings of the ESSCIRC (ESSCIRC) - Bordeaux Convention Center, Bordeaux, Frankrijk Duur: 17 sep. 2012 → 21 sep. 2012 Congresnummer: 38 |
Congres
Congres | 2012 Proceedings of the ESSCIRC (ESSCIRC) |
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Verkorte titel | ESSCIRC 2012 |
Land/Regio | Frankrijk |
Stad | Bordeaux |
Periode | 17/09/12 → 21/09/12 |
Ander | The 38th European Solid-State Circuits Conference (ESSCIRC 2012) 17-21 September 2012, Bordeaux, France, |