A reconfigurable fractional interpolation hardware for VVC motion compensation

Hasan Azgin, Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

20 Citaten (Scopus)

Samenvatting

Fractional interpolation is one of the most computationally complex parts of video compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a reconfigurable VVC fractional interpolation hardware for motion compensation is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware for motion compensation in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 66 quad full HD (3840x2160) frames per second. It has up to 77% less power consumption than baseline VVC fractional interpolation hardware.

Originele taal-2Engels
Titel2018 21st Euromicro Conference on Digital System Design (DSD)
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's99-103
Aantal pagina's5
ISBN van elektronische versie978-1-5386-7377-5
DOI's
StatusGepubliceerd - 15 okt. 2018
Extern gepubliceerdJa
Evenement21st Euromicro Conference on Digital System Design, DSD 2018 - Prague, Tsjechië
Duur: 29 aug. 201831 aug. 2018
Congresnummer: 21
http://dsd-seaa2018.fit.cvut.cz/dsd/

Congres

Congres21st Euromicro Conference on Digital System Design, DSD 2018
Verkorte titelDSD 2018
Land/RegioTsjechië
StadPrague
Periode29/08/1831/08/18
Internet adres

Bibliografische nota

Publisher Copyright:
© 2018 IEEE.

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