Samenvatting
Fractional interpolation is one of the most computationally complex parts of video compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a reconfigurable VVC fractional interpolation hardware for motion compensation is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware for motion compensation in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 66 quad full HD (3840x2160) frames per second. It has up to 77% less power consumption than baseline VVC fractional interpolation hardware.
Originele taal-2 | Engels |
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Titel | 2018 21st Euromicro Conference on Digital System Design (DSD) |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Pagina's | 99-103 |
Aantal pagina's | 5 |
ISBN van elektronische versie | 978-1-5386-7377-5 |
DOI's | |
Status | Gepubliceerd - 15 okt. 2018 |
Extern gepubliceerd | Ja |
Evenement | 21st Euromicro Conference on Digital System Design, DSD 2018 - Prague, Tsjechië Duur: 29 aug. 2018 → 31 aug. 2018 Congresnummer: 21 http://dsd-seaa2018.fit.cvut.cz/dsd/ |
Congres
Congres | 21st Euromicro Conference on Digital System Design, DSD 2018 |
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Verkorte titel | DSD 2018 |
Land/Regio | Tsjechië |
Stad | Prague |
Periode | 29/08/18 → 31/08/18 |
Internet adres |
Bibliografische nota
Publisher Copyright:© 2018 IEEE.