A pseudo-dynamic comparator for error detection in fault tolerant architectures

D.A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

7 Citaten (Scopus)

Samenvatting

Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.
Originele taal-2Engels
Titel2012 IEEE 30th VLSI Test Symposium (VTS)
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's50-55
Aantal pagina's6
ISBN van elektronische versie978-1-4673-1074-1
ISBN van geprinte versie978-1-4673-1073-4
DOI's
StatusGepubliceerd - 5 jul. 2012
Extern gepubliceerdJa
Evenement30th VLSI Test Symposium (VTS) 2012 - Maui, Verenigde Staten van Amerika
Duur: 23 apr. 201225 apr. 2012

Congres

Congres30th VLSI Test Symposium (VTS) 2012
Land/RegioVerenigde Staten van Amerika
StadMaui
Periode23/04/1225/04/12

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