A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Yang Liu, Zhiqun Li, Hao Gao

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

Samenvatting

This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

Originele taal-2Engels
TitelEuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's221-224
Aantal pagina's4
ISBN van elektronische versie9782874870606
StatusGepubliceerd - 10 jan 2021
Evenement15th European Microwave Integrated Circuits Conference, EuMIC 2020 - Utrecht, Nederland
Duur: 11 jan 202112 jan 2021

Congres

Congres15th European Microwave Integrated Circuits Conference, EuMIC 2020
LandNederland
StadUtrecht
Periode11/01/2112/01/21

Vingerafdruk Duik in de onderzoeksthema's van 'A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver'. Samen vormen ze een unieke vingerafdruk.

Citeer dit