A novel test time reduction algorithm for test architecture design for core-based system chips

Sandeep K. Goel, E.J. Marinissen

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

7 Citaten (Scopus)

Samenvatting

This paper deals with the design of SoC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail architecture for a given SoC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SoCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
Originele taal-2Engels
TitelProceedings of the Seventh IEEE European Test Workshop
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's7-12
Aantal pagina's6
ISBN van geprinte versie0-7695-1715-3
DOI's
StatusGepubliceerd - 2002
Extern gepubliceerdJa
Evenement7th IEEE European Test Workshop - Corfu, Griekenland
Duur: 26 mei 200229 mei 2002

Congres

Congres7th IEEE European Test Workshop
Land/RegioGriekenland
StadCorfu
Periode26/05/0229/05/02

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