This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-VP-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.
|Titel||Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia|
|Plaats van productie||Piscataway|
|Uitgeverij||Institute of Electrical and Electronics Engineers|
|ISBN van geprinte versie||978-1-4244-5090-9|
|Status||Gepubliceerd - 2009|
Abdinia, S., & Yavari, M. (2009). A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques. In Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia (blz. 395-398). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICECS.2009.5410909