A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO

Samuel M. Palermo; J. Pineda de Gyvez

doi:10.1109/MWSCAS.2000.952881

A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO

Samuel M. Palermo, J. Pineda de Gyvez

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

6 Citaten (Scopus)

301 Downloads (Pure)

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A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 µm CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply

Originele taal-2	Engels
Titel	Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, 8-11 August 200, Lansing, Michigan
Plaats van productie	New York
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	818-821
Volume	2
ISBN van geprinte versie	0-7803-6475-9
DOI's	https://doi.org/10.1109/MWSCAS.2000.952881
Status	Gepubliceerd - 2000
Extern gepubliceerd	Ja

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10.1109/MWSCAS.2000.952881

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Palermo, S. M., & Pineda de Gyvez, J. (2000). A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO. In Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, 8-11 August 200, Lansing, Michigan (Vol. 2, blz. 818-821). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/MWSCAS.2000.952881

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title = "A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO",

abstract = "A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 µm CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply",

author = "Palermo, {Samuel M.} and {Pineda de Gyvez}, J.",

year = "2000",

doi = "10.1109/MWSCAS.2000.952881",

language = "English",

isbn = "0-7803-6475-9",

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Palermo, SM & Pineda de Gyvez, J 2000, A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO. in Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, 8-11 August 200, Lansing, Michigan. vol. 2, Institute of Electrical and Electronics Engineers, New York, blz. 818-821. https://doi.org/10.1109/MWSCAS.2000.952881

A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO. / Palermo, Samuel M.; Pineda de Gyvez, J.
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, 8-11 August 200, Lansing, Michigan. Vol. 2 New York: Institute of Electrical and Electronics Engineers, 2000. blz. 818-821.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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T1 - A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO

AU - Palermo, Samuel M.

AU - Pineda de Gyvez, J.

PY - 2000

Y1 - 2000

N2 - A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 µm CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply

AB - A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 µm CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply

U2 - 10.1109/MWSCAS.2000.952881

DO - 10.1109/MWSCAS.2000.952881

M3 - Conference contribution

SN - 0-7803-6475-9

VL - 2

SP - 818

EP - 821

BT - Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, 8-11 August 200, Lansing, Michigan

PB - Institute of Electrical and Electronics Engineers

CY - New York

ER -

A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO

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