A method and a device for testing a memory array in which fault response is compressed.

E.J. Marinissen (Uitvinder), G.E.A. Lousberg (Uitvinder), P. Wielage (Uitvinder)

Onderzoeksoutput: OctrooiOctrooi-publicatie

Samenvatting

A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row- and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.
Originele taal-2Engels
OctrooinummerEP1116241
IPCG11C 29/ 44 A I
Prioriteitsdatum17/07/00
StatusGepubliceerd - 18 jul 2001
Extern gepubliceerdJa

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