A manufacturable sub-50nm PMOSFET technology

J. J.G.P. Loo, Y. V. Ponomarev, M. Kaiser, M. A. Verheijen, F. N. Cubaynes, C. J.J. Dachs

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review


One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.

Originele taal-2Engels
TitelEuropean Solid-State Device Research Conference
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's4
ISBN van geprinte versie2914601018
StatusGepubliceerd - 1 jan 2001
Extern gepubliceerdJa
Evenement31st European Solid-State Device Research Conference, ESSDERC 2001 - Nuremberg, Duitsland
Duur: 11 sep 200113 sep 2001


Congres31st European Solid-State Device Research Conference, ESSDERC 2001


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