A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

Wim van der Wel; Ronald Koster; Sander C.L. Jansen; Freek W. Ahlrichs; Peter G.M. Baltus; Gideon W. Kant

doi:10.1109/16.535347

A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

Wim van der Wel, Ronald Koster, Sander C.L. Jansen, Freek W. Ahlrichs, Peter G.M. Baltus, Gideon W. Kant

Onderzoeksoutput: Bijdrage aan tijdschrift › Tijdschriftartikel › Academic › peer review

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A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 μm-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature.

Originele taal-2	Engels
Artikelnummer	535347
Pagina's (van-tot)	1539-1546
Aantal pagina's	8
Tijdschrift	IEEE Transactions on Electron Devices
Volume	43
Nummer van het tijdschrift	9
DOI's	https://doi.org/10.1109/16.535347
Status	Gepubliceerd - 1996
Extern gepubliceerd	Ja

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title = "A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier",

abstract = "A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 μm-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature.",

author = "{van der Wel}, Wim and Ronald Koster and Jansen, {Sander C.L.} and Ahlrichs, {Freek W.} and Baltus, {Peter G.M.} and Kant, {Gideon W.}",

year = "1996",

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T1 - A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

AU - van der Wel, Wim

AU - Koster, Ronald

AU - Jansen, Sander C.L.

AU - Ahlrichs, Freek W.

AU - Baltus, Peter G.M.

AU - Kant, Gideon W.

PY - 1996

Y1 - 1996

N2 - A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 μm-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature.

AB - A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 μm-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature.

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A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

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