A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA

Recently, SRAM-based FPGAs are widely used in aeronautic and space systems. As the adverse effects of radiations in space are much higher than in the Earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. However, fault tolerance techniques might introduce additional penalties in area, power, performance and design time. In order to compromise between the overhead introduced by these techniques and system fault tolerance, a generic methodology for calculating design sensitivity to Single-Event Upset (SEU) is proposed in this paper. Separate schema and test-bench for evaluating effects of SEU in various types of FPGA memory are proposed in which both the raw device error rate and the vulnerability characteristic of the specific application mapped on the device are taken into account. Experimental results show that using our model in order to selectively add Triple Modular Redundancy (TMR) improve the design robustness only 18% less than full TMR while roughly introduces 69% less redundancy compared to full TMR for Fast Fourier Transform (FFT).