A formal model of clock domain crossing and automated verification of time-triggered hardware

J. Schmaltz

doi:10.1109/FMCAD.2007.2

A formal model of clock domain crossing and automated verification of time-triggered hardware

J. Schmaltz

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

Originele taal-2	Engels
Titel	Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings)
Uitgeverij	IEEE Computer Society
Pagina's	223-230
DOI's	https://doi.org/10.1109/FMCAD.2007.2
Status	Gepubliceerd - 2007

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10.1109/FMCAD.2007.2

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@inproceedings{d0f53dc73eb64930b38f4f5e0c7e243b,

title = "A formal model of clock domain crossing and automated verification of time-triggered hardware",

author = "J. Schmaltz",

year = "2007",

doi = "10.1109/FMCAD.2007.2",

language = "English",

pages = "223--230",

booktitle = "Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings)",

publisher = "IEEE Computer Society",

address = "United States",

}

A formal model of clock domain crossing and automated verification of time-triggered hardware. / Schmaltz, J.

Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings). IEEE Computer Society, 2007. blz. 223-230.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

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AU - Schmaltz, J.

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DO - 10.1109/FMCAD.2007.2

M3 - Conference contribution

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EP - 230

BT - Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings)

PB - IEEE Computer Society

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