Samenvatting
The subject of this paper is an algorithm generating topological layouts for VLSI-circuits that are specified by means of programs. A topological layout, which is both a metric-free and a material-free layout, is an intermediate step in the process of converting a program into a silicon chip. The algorithm described in this paper is based upon a bottom-up approach, while lazy evaluation, constituted by the postponement of the construction of some connections, guarantees a flexible connecting to different environments.
Originele taal-2 | Engels |
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Pagina's (van-tot) | 49-59 |
Aantal pagina's | 11 |
Tijdschrift | Integration : the VLSI Journal |
Volume | 3 |
Nummer van het tijdschrift | 1 |
DOI's | |
Status | Gepubliceerd - 1985 |