A background calibration technique based on limit cycles for reconfigurable sigma delta modulators

Reconfigurable ADCs bring a lot of functionality, high added value while sharing the development time and cost for each targeted application. Sigma Delta Modulators (SDMs) are very popular for their suitability for a wide range of
applications. While individual SDMs can be tailored towards specific applications, a reconfigurable SDM addresses several of them at the same time. Due to their complexity (introduced by the programmability) and the limitations imposed by PVT variations, calibration is essential. To this effect, we introduce a new background calibration technique based on the limit cycle model of SDMs. We show how a simple counting and categorization of output bit-patterns can be used for measurement and correction/adjustment of the loop filter in the presence of multiple inaccuracies or changing operation conditions. The
calibration scheme is demonstrated with measurement results from a test chip. The chip implements a 3rd order reconfigurable SDM for ultra-low bio-sensor current measurements. The reconfigurablity, coupled with the calibration scheme, allows a widely programmable bandwidth and dynamic range, making it useful for a variety of applications.