A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset

M. Liu, A.H.M. van Roermund, P.J.A. Harpe

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

12 Citaten (Scopus)
3 Downloads (Pure)

Samenvatting

In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also applied to the 2 MSBs of the DAC to enhance the linearity to 88dB SFDR. The SAR ADC operates at 0.8V VDD and 40kS/s, achieving an SNDR of 64.2dB and a FoM of 7.1fJ/conversion-step.
Originele taal-2Engels
TitelEuropean Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's409-412
ISBN van elektronische versie978-1-5090-2972-3
ISBN van geprinte versie978-1-5090-2973-0
DOI's
StatusGepubliceerd - 2016
Evenement42th European Solid-State Circuits Conference (ESSCIRC 2016) - Lausanne, Zwitserland
Duur: 12 sep 201615 dec 2016
Congresnummer: 42

Congres

Congres42th European Solid-State Circuits Conference (ESSCIRC 2016)
Verkorte titelESSCIRC2016
LandZwitserland
StadLausanne
Periode12/09/1615/12/16

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