A 71 GHz 3-Stage Rectifier with 8% Efficiency

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This paper presents a 71 GHz fully on-chip 3-stage inductor-peaked rectifier in 65-nm CMOS technology. The multistage rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, sensitivity and efficiency problems of the mm-wave rectifier are discussed and a 3-stage inductor-peaked rectifier structure is proposed and realized. By cascading inductor-peaked rectifiers with optimized layout, the measured rectifier provide 1 V output voltage with 5 dBm input power at 71 GHz, it also reaches 8% efficiency with 720 μA current load. Compared to previous work of 45 GHz rectifier with 1.2% efficiency [1] and 62 GHz with 7% efficiency [2], this work provides higher efficiency and higher output voltage for mm-wave wireless power receivers.

Originele taal-2Engels
Titel2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's3
ISBN van elektronische versie9781728107165
DOI's
StatusGepubliceerd - 1 mei 2019
Evenement6th IEEE MTT-S International Wireless Symposium - Guangzhou, China
Duur: 19 mei 201922 mei 2019
https://10times.com/ieee-iws

Congres

Congres6th IEEE MTT-S International Wireless Symposium
Verkorte titelIEEE IWS 2019
LandChina
StadGuangzhou
Periode19/05/1922/05/19
Internet adres

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Citeer dit

Gao, H., & Baltus, P. (2019). A 71 GHz 3-Stage Rectifier with 8% Efficiency. In 2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings [8804129] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/IEEE-IWS.2019.8804129