A 680nA ECG acquisition IC for leadless pacemaker applications

L. Yan, P.J.A. Harpe, V.R. Pamula, M. Osawa, Y. Harada, K. Tamiya, C. Van Hoof, R.F. Yazicioglu

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29 Citaten (Scopus)
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A sub- µW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR >90 dB, PSRR >80 dB, an input-referred noise of 4.9 µVrms in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR >6 dB.
Originele taal-2Engels
Pagina's (van-tot)779-786
Aantal pagina's8
TijdschriftIEEE Transactions on Biomedical Circuits and Systems
Nummer van het tijdschrift6
StatusGepubliceerd - 2014

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