A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit

P.J.A. Harpe, A. Zanikopoulos, J.A. Hegt, A.H.M. Roermund, van

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

10 Citaten (Scopus)


In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply
Originele taal-2Engels
TitelProceedings of the 24th IEEE Norchip 2006 Conference
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's4
ISBN van geprinte versie1-4244-0772-9
StatusGepubliceerd - 2006
EvenementIEEE Norchip 2006 - Linkoping, Zweden
Duur: 20 nov 200621 nov 2006


CongresIEEE Norchip 2006
AnderIEEE Norchip 2006, Likoping, Sweden, November 20,21


Duik in de onderzoeksthema's van 'A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit'. Samen vormen ze een unieke vingerafdruk.

Citeer dit