Samenvatting
A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in the new delay cells, achieving an ENOB of 4.85bit with 1.5GHz ERBW. This ADC consumes 2.7mW at a 1V supply, enabling a FoM of 93fJ/conversion-step. At 0.8V, it can work at 0.5GS/s. Even compared to the state-of-the-art of well-established architectures, it achieves similar power-efficiency.
Originele taal-2 | Engels |
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Titel | Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada |
Plaats van productie | Piscataway |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Pagina's | 487-490 |
DOI's | |
Status | Gepubliceerd - 2012 |
Evenement | RFIC/IMSWFF (Advances in reconfirgurable RF systems and materials) 2012 - Montréal, Canada Duur: 17 jun. 2012 → 19 jun. 2012 |
Congres
Congres | RFIC/IMSWFF (Advances in reconfirgurable RF systems and materials) 2012 |
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Verkorte titel | RFIC 2012 |
Land/Regio | Canada |
Stad | Montréal |
Periode | 17/06/12 → 19/06/12 |
Ander | Radio Frequency Integrated Circuits Symposium (RFIC) |