A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

M. Ding, P.J.A. Harpe, Y.-H. Liu, B. Büsze, K.J.P. Philips, H.W.H. Groot, de

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

30 Citaten (Scopus)
9 Downloads (Pure)

Samenvatting

Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.
Originele taal-2Engels
TitelProceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's460-461
ISBN van geprinte versie978-1-4799-6223-5
DOI's
StatusGepubliceerd - 2015
Evenement62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015) - San Francisco Marriott, San Francisco, Verenigde Staten van Amerika
Duur: 22 feb 201526 feb 2015
Congresnummer: 62

Congres

Congres62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015)
Verkorte titelISSCC 2015
LandVerenigde Staten van Amerika
StadSan Francisco
Periode22/02/1526/02/15
AnderSolid- State Circuits Conference - (ISSCC), 2015 IEEE International

    Vingerafdruk

Citeer dit

Ding, M., Harpe, P. J. A., Liu, Y-H., Büsze, B., Philips, K. J. P., & Groot, de, H. W. H. (2015). A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. In Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California (blz. 460-461). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2015.7063125