Samenvatting
An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm2.
Originele taal-2 | Engels |
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Titel | 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Aantal pagina's | 2 |
ISBN van elektronische versie | 9781728199429 |
DOI's | |
Status | Gepubliceerd - jun. 2020 |
Evenement | 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, Verenigde Staten van Amerika Duur: 16 jun. 2020 → 19 jun. 2020 |
Congres
Congres | 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 |
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Land/Regio | Verenigde Staten van Amerika |
Stad | Honolulu |
Periode | 16/06/20 → 19/06/20 |
Financiering
Acknowledgements This project (PHOENIX) has received funding from the EU’s Horizon 2020 research and innovation programme under grant agreement No 665347. References