A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

12 Citaten (Scopus)

Samenvatting

An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm2.

Originele taal-2Engels
Titel2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's2
ISBN van elektronische versie9781728199429
DOI's
StatusGepubliceerd - jun. 2020
Evenement2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, Verenigde Staten van Amerika
Duur: 16 jun. 202019 jun. 2020

Congres

Congres2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Land/RegioVerenigde Staten van Amerika
StadHonolulu
Periode16/06/2019/06/20

Financiering

Acknowledgements This project (PHOENIX) has received funding from the EU’s Horizon 2020 research and innovation programme under grant agreement No 665347. References

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