A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Haoming Xin; Kevin Pelzers; Peter Baltus; Eugenio Cantatore; Pieter Harpe

doi:10.1109/VLSICircuits18222.2020.9162817

A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Haoming Xin, Kevin Pelzers, Peter Baltus, Eugenio Cantatore, Pieter Harpe

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

Samenvatting

An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm².

Originele taal-2	Engels
Titel	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	2
ISBN van elektronische versie	9781728199429
DOI's	https://doi.org/10.1109/VLSICircuits18222.2020.9162817
Status	Gepubliceerd - jun 2020
Evenement	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, Verenigde Staten van Amerika Duur: 16 jun 2020 → 19 jun 2020

Congres

Congres	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Land	Verenigde Staten van Amerika
Stad	Honolulu
Periode	16/06/20 → 19/06/20

Toegang tot document

10.1109/VLSICircuits18222.2020.9162817

Link to publication in Scopus

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Citeer dit

Xin, H., Pelzers, K., Baltus, P., Cantatore, E., & Harpe, P. (2020). A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings [9162817] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSICircuits18222.2020.9162817

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title = "A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse",

abstract = "An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm2.",

author = "Haoming Xin and Kevin Pelzers and Peter Baltus and Eugenio Cantatore and Pieter Harpe",

year = "2020",

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language = "English",

booktitle = "2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings",

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Xin, H , Pelzers, K , Baltus, P , Cantatore, E & Harpe, P 2020, A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. in 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings., 9162817, Institute of Electrical and Electronics Engineers, 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, Verenigde Staten van Amerika, 16/06/20. https://doi.org/10.1109/VLSICircuits18222.2020.9162817

A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. / Xin, Haoming ; Pelzers, Kevin ; Baltus, Peter ; Cantatore, Eugenio ; Harpe, Pieter.

2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers, 2020. 9162817.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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