A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K. Makinwa, L. Breems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

1 Citaat (Scopus)

Samenvatting

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

Originele taal-2Engels
Titel2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina'sC230-C231
Aantal pagina's2
ISBN van elektronische versie978-4-86348-720-8
DOI's
StatusGepubliceerd - 1 jun 2019
Evenement33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
Duur: 9 jun 201914 jun 2019

Congres

Congres33rd Symposium on VLSI Circuits, VLSI Circuits 2019
LandJapan
StadKyoto
Periode9/06/1914/06/19

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Citeer dit

Cenci, P., Bolatkale, M., Rutten, R., Ganzerli, M., Lassche, G., Makinwa, K., & Breems, L. (2019). A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (blz. C230-C231). [8778176] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.23919/VLSIC.2019.8778176