A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR

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Samenvatting

This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The ADC uses dynamically biased comparators, which require minimal power when the input voltage is far away from a decision threshold. This results in >10x better power efficiency compared to prior LC-ADCs when converting sparse signals. In a 16 kHz bandwidth, the LC-ADC achieves a 61.4 dB SNDR resulting in an efficiency of 3 fJ/conv.step for sparse input signals.

Originele taal-2Engels
Titel2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
UitgeverijInstitute of Electrical and Electronics Engineers
HoofdstukC18-1
Aantal pagina's2
ISBN van elektronische versie978-4-86348-806-9
DOI's
StatusGepubliceerd - 24 jul. 2023
Evenement2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duur: 11 jun. 202316 jun. 2023

Congres

Congres2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Land/RegioJapan
StadKyoto
Periode11/06/2316/06/23

Bibliografische nota

Funding Information:
This work is supported by the Dutch Research Council (NWO) under Project 17608.

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